1) Field of the Invention
This invention relates generally to structures and methods for making semiconductor devices and more particularly to the structures and methods for semiconductor devices having stress layers.
2) Description of the Prior Art
Conventional transistor scaling is facing immense difficulties. One way to enhance transistor performance is through the Improvements in performances of MOS transistors and CMOS have been made by shrinkage or scaling down thereof, for example, shortening a channel length and a reduction in thickness of a gate insulating film. A reduction in thickness of the gate insulating film and a minimum size or dimension for process have become closer to the limitations. A further improvement in performance can not depend upon the limited shrinkage or scaling down of the device, but should depend upon any other measures than the shrinkage or scaling down of the device.
One of the improvements in performance of the device is a technique of applying a stress to a channel region for improving a carrier mobility, so called strained-Si channel technique. The use of strain-Si to improve carrier mobility which gives raise to higher drive current. There are various ways to induce strain in the conduction channel. These include pseudomorphically growing strain Si on virtual SiGe substrate, using SiGe source/drain stressors or process-induced strained Si.
There is a need for improved strain-Si structures and process to improve device performance.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
US20050032275A1: Toda—Mos semiconductor device—Semiconductor device including p-channel MOS transistor, has larger compressive strain in channel direction than in width direction of gate, and silicon nitride insulating film.
US20040235236A1:—Hoffmann, et al.—Integrated circuit with improved channel stress properties and a method for making it—Integrated circuit comprises silicate glass layer formed only on p-type metal oxide semiconductor transistor or n-type metal oxide semiconductor transistor and etch stop layer formed on silicate glass layer
US20040142545A1: Inventor: Ngo—Semiconductor with tensile strained substrate and method of making the same—Formation of metal oxide semiconductor field effect transistor involves high compression deposition that increases tensile strain in silicon layer—An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.
US20020045325A1: Kuhn et al.—Thin tensile layers in shallow trench isolation and method of making same—: Formation of isolation trench involves forming film on recess sidewall under conditions that will cause the film to have tensile load, and filling the recess with material that imparts compressive load
U.S. Pat. No. 6,573,172: En et al.—Methods for improving carrier mobility of PMOS and NMOS devices Fabrication of semiconductor device by forming P-channel and N-channel metal oxide semiconductor transistors in wafer, forming tensile film on P-channel transistor and forming compressive film on N-channel transistor.
US20040253791A1: Sun et al.—Methods of fabricating a semiconductor device having MOS transistor with strained channel—Fabrication of semiconductor device, by forming stress layer on substrate having transistor, and annealing stress layer to convert physical stress of stress layer into tensile stress or increase tensile stress of stress layer.